Saeed A, Ali A, Saeed A, Hassan I, Shukla NK, Abdul Muqeet M, Birla S. Design, Synthesis, and Testbench Verification of High Order Decoder Circuits Using VerilogHDL. jmmf [Internet]. 2023 Jun. 1 [cited 2024 May 2];71(4):520-2. Available from: http://www.informaticsjournals.com/index.php/jmmf/article/view/33929