Saeed, Abdulkhaliq, Amjed Ali, Abdulaziz Saeed, Ibrahim Hassan, Neeraj Kumar Shukla, M. Abdul Muqeet, and Shilpi Birla. 2023. “Design, Synthesis, and Testbench Verification of High Order Decoder Circuits Using VerilogHDL”. Journal of Mines, Metals and Fuels 71 (4):520-22. https://doi.org/10.18311/jmmf/2023/33929.