SAEED, A.; ALI, A.; SAEED, A.; HASSAN, I.; SHUKLA, N. K.; ABDUL MUQEET, M.; BIRLA, S. Design, Synthesis, and Testbench Verification of High Order Decoder Circuits Using VerilogHDL. Journal of Mines, Metals and Fuels, [S. l.], v. 71, n. 4, p. 520–522, 2023. DOI: 10.18311/jmmf/2023/33929. Disponível em: http://www.informaticsjournals.com/index.php/jmmf/article/view/33929. Acesso em: 2 may. 2024.