Design, Synthesis, and Testbench Verification of High Order Decoder Circuits Using VerilogHDL

Abstract

The decoder is an integral part of modern memory, processors. In this work, a 5 to 32 and 6 to 64 decoders have been designed and characterized using low-order decoders for the state-of-the-art digital systems. The Design and Synthesis work have been executed at the Register Transfer Level (RTL) and the Testbench based Verification has been performed to ensure the functional correctness of the designs with timing constraints. RTL Coding is done at VerilogHDL Std. IEEE 1364-2001 and IEEE 1364-2005. It is observed that the 5 to 32 and 6 to 64 order decoders utilize the highest 15% and 30% bonded IOBs where the 2 to 4 decode 2% only. It is found that the 6 to 64 decoders have 5% higher delay to 5 to 32 decoders whereas the 5 to 32 decoder has 5.5% more logic delay and 9.1% less route delay as compared to the 6 to 64 decoders.