CMOS Analog Multipliers : Low Power Design Strategies and the Impact of Threshold Voltage Variations

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Authors

  • Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan ,IN
  • Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan ,IN
  • Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan ,IN
  • Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan ,IN
  • Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan ,IN

DOI:

https://doi.org/10.18311/jmmf/2023/33921

Keywords:

CMOS Analog Multipliers, Analog Circuits, Process Variations, Reliability, Monte Carlo Models.

Abstract

Due to process variations in key MOSFET parameters like channel length, width, threshold voltage (Vth) etc. the output of analog circuits is affected to a large extent. In this work, our aim is to examine the yield of a typical CMOS analog multiplier designed at 65 nm technology node due to Vth variations and figure out the variation in key parameters by using Gaussian distribution - Monte Carlo model. We have considered a typical Quad multiplier configuration to examine the variability in the multiplier output under 2% and 5% variation in threshold voltage of the 65 nm bulk BSIM model. Using the case of Gaussian distribution - Monte Carlo simulation, the standard deviation in the multiplier output is found to be 1.4 mV for both 2% and 5% variations. A good yield prediction with variation of 2% and 5% in Vth is possible at 65 nm technology node.

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Published

2023-06-01

How to Cite

Vijay, A., Duari, C., Sharma, M. K., Garg, L., & Singh, A. K. (2023). CMOS Analog Multipliers : Low Power Design Strategies and the Impact of Threshold Voltage Variations. Journal of Mines, Metals and Fuels, 71(4), 502–507. https://doi.org/10.18311/jmmf/2023/33921

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