A novel filter for three-phase power factor correction voltage feedback loop under heavy DC voltage ripple condition

THD and the amplitude balance of three-phase input current are an important index for the performance of three-phase power factor correction (PFC). In general, when the hardware and the load of three-phase PFC are confirmed, the THD and amplitude balance of three-phase input current mainly depend on voltage and current feedback loop of PFC. Firstly, this paper designs the traditional voltage and current feedback loop for three-phase PFC according to traditional small signal theory. Secondly, this paper studies the designing difficulty of large dc voltage ripple for PFC voltage controller and puts forward a new dc voltage ripple filter which can eliminate the ac component of sampling dc bus voltage. Finally, this paper proposes a novel filter with dc voltage ripple frequency adaption function to copy with the frequency variety of the voltage ripple caused by the change of the output inverter frequency. With the help of the proposed algorithm the distortion of three-phase 3 input current reference decreases rapidly, therefore, the low THD and good amplitude balance of three phase input current will be achieved.

THD and the amplitude balance of three-phase input current are an important index for the performance of three-phase power factor correction (PFC). In general, when the hardware and the load of three-phase PFC are confirmed, the THD and amplitude balance of three-phase input current mainly depend on voltage and current feedback loop of PFC. Firstly, this paper designs the traditional voltage and current feedback loop for three-phase PFC according to traditional small signal theory. Secondly, this paper studies the designing difficulty of large dc voltage ripple for PFC voltage controller and puts forward a new dc voltage ripple filter which can eliminate the ac component of sampling dc bus voltage. Finally, this paper proposes a novel filter with dc voltage ripple frequency adaption function to copy with the frequency variety of the voltage ripple caused by the change of the output inverter frequency. With the help of the proposed algorithm the distortion of three-phase 3 input current reference decreases rapidly, therefore, the low THD and good amplitude balance of three phase input current will be achieved.

Introduction
T he objective of power factor correction (PFC) is to force the input current in phase with the line voltage. Boost circuit is an excellent choice for the power stage of a power factor corrector because the inductor current of boost can be designed in continuous mode which produces the lowest level of conducted noise and the best input current waveform [1]. By the way of controlling the duty of boost circuit, the PFC feedback loop controls dc bus voltage around the dc voltage reference and forces input current in phase with the utility voltage. Therefore, the PFC feedback loop between dc voltage control and input current control has no decoupling function and has inter-disturbance between the voltage feedback loop and the current feedback loop. In order to get rid of the sampling ripple voltage in dc feedback sampling voltage, the bandwidth of voltage feedback loop has to decline. But with the drop of bandwidth the transient performance of PFC will become worse. By way of solving the contradiction many methods are put forward [1][2][3][4]. In addition the notch filter is studied [5][6]. But the notch filter can only filter the specified harmonic and has some disadvantages to feedback loop of PFC. A comb filter is also researched [7.8]. But it needs large calculating time and is not suitable for application. Anyhow, if a notch filter or comb filter is usually implemented without ripple voltage frequency adaption function. Therefore, this paper first designed the conventional PFC controller in terms of traditional small signal theory. Then a novel harmonic suppression filter with ripple voltage frequency adaption function is put forward and its feasibility is confirmed in theory. Finally the simulation results verify the theoretical analysis and the validity of the control scheme. Fig.1 shows a single-phase output inverter with three-phase input topology with three PFC circuits. Because the sum of three-phase instantaneous input power is almost dc component but the output power is ac component. According to energy conservation theory this inverter with three-phase input single-phase output topology causes large ripple voltage which usually causes high THD and the serious amplitude unbalance of three-phase current. Because three boost circuits are same and independent, then this paper only analyzes the boost circuit in phase A. In phase A PFC circuit, the input current i a is controlled by changing the conduction time of transistor Qa. When transistor Qa is on, the power supply is short-circuited through the inductor La; when transistor Qa is turned off, the inductor current i a cannot be interrupted abruptly and flows through diode Da, charging dc bus capacitor C.

Design of tradition PFC feedback loop
According to the on and off state, this paper can get state-space average equation of A phase boost circuit is shown as follows: ... (1)  where V a , i a , V dc , Z a , D a stand for utility voltage, inductor current, dc voltage, equivalent load and duty in A phase respectively. Considering the perturbation at i a , V dc and D a in terms of small signal theory [9,10], this paper defines ignores the second order components and does Laplace transform to the perturbation functions. Finally the transfer of the inductor current perturbation i^a(s) to the switching perturbation D a (s) and the transfer of dc voltage perturbation V dc (s) to the inductor current perturbation can be achieved as following: ... (2) Supposing the dc bus voltage reference is 360V, the nominal inductance L a is 1.2mH, the dc bus capacitance C is 6000uF, the switching frequency is 20 kHz, and the total output power of three-phase PFC is 8000W. So the equation (2) can be written as following: ... (3) As we all know that the PFC usually adopts double feedback loop controlling scheme to regulate the input current in phase with the input utility voltage. The output of the voltage feedback loop is V m which represents the conductance of the total boost circuits. V m is required to be constant value at steady state, so this paper has to damp the designed. At last for voltage loop controller an assumption should be made that the zero point (Z a (1-D a ) 2 /L a ) in V dc (s)/ î a (s) is very far from virtual axis, so the influence of the zero point can be ignored in the PFC voltage feedback loop.
Because PFC is nonlinear control, we should consider input utility voltage for different phase and amplitude, different load, the inductor value in different current, and so on. Based on that, this paper should analyze its different working condition. If the controller meets the steady requirements for all the conditions mentioned above, we can say that the controller is practical. So, this paper only shows a bode plot of voltage and current loop at full resistance load condition. The voltage controller G v (s) and the current controller G i (s) are show in formula (4): ... (4) The open loop bode plot of the voltage feedback loop and the current feedback loop are shown in Figs.2 and 3 individually.

Digital filter for voltage feedback loop
The specified transfer function of the second-order BPF in the Laplace domain is expressed as: ... (5) Where  n is the natural angular frequency which should be equal to the frequency of dc voltage ripple and k is a coefficient deciding the bandwidth of the BPF. Fig.1 A single-phase output inverter with three-phase input topology with PFC function dc voltage ripple by the voltage feedback loop. Usually, the bandwidth of the voltage feedback loop is required to be designed at about 25Hz, but too low band-width may worsen transient response. As a result, this paper makes compromise between the steady behaviour and the transient response.
The band-width of current feedback loop f c should be smaller than the ratio between the switching frequency f sw and 2 (f c < f sw /2). Considering the delay and the nonlinear factors in the controlling system, this paper designs the bandwidth of the current feedback loop at around 2.5 kHz. Taking the precision of controller into account the sequence of controller is that the current loop controller should be first The bode plot of the BPF ( n =200) is shown in Fig.4. It is obvious to see that the filter shows itself as unit gain with zero phase-shift at 100Hz. the smaller value of k will have a narrower window at 100 Hz. In addition, the low frequency and high frequency utility voltage harmonics are significantly reduced rapidly with small value of k.
According to formula (5) the proposed three-phase PFC block diagram with novel filter dc eliminating voltage ripple structure is shown in Fig.5. Therefore, making use of BPF in dc bus voltage feedback loop can attenuate the dc voltage ripple synchronously. be studied so as to broaden the range of applications of the proposed dc voltage ripple filter. A full-pass filter (APF) (s- n )/(s+ n ) is used to realize ripple frequency adaptation algorithm.
The bode plot of the APF ( n =200) is shown in Fig.6. On the assumption that an extra phase lock loop track the phase of output inverter voltage with 50Hz frequency which can cause dc voltage ripple of 200Hz frequency in topology of Fig.1. Therefore the phase lock signal (cos) act as the input of the APF, then the output signals of the APF can be expressed as, cos() where  is the delay angle of APF at  n is equal to 200.
According to Fig.6, if the estimated frequency of the filter  n is equal to the real frequency of dc ripple voltage, then cos() will be equal to sin. Therefore, if the estimated frequency  n is bigger than the dc voltage ripple frequency the lag phase  will be smaller than 90 o , which means that the phase of cos() is in front of the phase of sin. On the other hand, if  n is smaller than dc bus voltage ripple frequency, the lag phase  will be larger than 90 o , which means that the phase of

DC bus voltage ripple frequency adaptation algorithm
Since the frequency of dc voltage ripple is two times the output inverter frequency in this three-phase input and single-phase output topology. If the frequency of output inverter changes the frequency of dc voltage ripple will be variable synchronously. Therefore, the parameter  n in BPF should be updated as soon as possible. A feasible frequency adaptation algorithm should Then, the error between sin and cos() can be used to estimate the dc voltage ripple angular frequency at zerocrossing point of sin adopting the following law using an integral controller, as shown in Fig.7.
Further, the dc voltage ripple frequency adaptation algorithm can be induced to the following relationship between the estimated angular frequencyand the dc voltage ripple frequency. Then, will be updated at zero-crossing point of.
... (6) Where the dc voltage ripple frequency  f is only a feed-forward component, and k i is the integral coefficient for the frequency adaption feedback loop. At positive zero crossing point the integral coefficient for the frequency adaption feedback loop is k i , otherwise at negative zero crossing point the integral coefficient for the frequency adaption feedback loop is -k i . The frequency adaptation integral controller calculates twice at every utility period.
Therefore, the control block diagram of the new dc voltage ripple filter arithmetic with frequency adaptation function for the threephase PFC topology in Fig.1 is shown in Fig.8.
With the help of the new dc voltage filter the ac component is cancelled in from the dc sampling voltage and the pure dc component is reserved. Therefore, for the voltage feedback loop of PFC the effect influenced by the dc voltage fluctuating is eliminated.

Simulation
In order to verify the proposed algorithm, simulations are implemented by the S-function in Matlab/Simulink. The main simulation parameters are same as mentioned above, in addition, the coefficient k in BPF is 0.1, the integral coefficientin frequency adaption is 0.6. To show the promising behaviours of the proposed method, two different utility frequency operation conditions are considered in the following simulation.
As has been mentioned above, an inverter with three-phase input and single-phase output has been built by Matlab/Simulink combined with controller written by C language to verify the analysis. Fig.9 shows the dc voltage waveform on the condition of 50Hz utility. Figs.10 and 11 show the difference of three phase 50Hz input current removing or adding the dc voltage filter. Fig.12 shows the dc voltage waveform on the condition of 55Hz utility. Figs.13 and 14 show the difference of three phase 55Hz input current removing or adding the dc voltage filter.
According the simulation waveforms the proposed dc voltage ripple filter has satisfactory performances at different frequency of dc ripple voltage.

Conclusion
This paper puts forward a novel three-phase dc voltage ripple filter with ripple voltage frequency adaption function in order to suppress the large dc voltage ripple for dc voltage feedback loop of PFC. The proposed filter can eliminate the ac component in sampling dc voltage and simplify the design of the PFC voltage feedback loop. The filter only need small calculation and can be carried out easily. Finally the simulation results verify the control scheme.